Under the dual influence of domestic demand and the international environment, many EDA companies have emerged in China over the past two years. According to incomplete statistics, there are now about 130 EDA companies in the country, of which more than 70 are engaged in chip design, bringing new innovations to the domestic EDA field from various fields.

Dr. Bai Geng, Executive President and Chief Technology Officer of Guowei Xin, said in his speech at the ICCAD 2023 Summit held recently that although domestic EDA companies have made breakthroughs in the development of some point tools, most are still limited to the front-end design, lacking more highly related, more complex back-end and manufacturing tools with the process factory.

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Guowei Xin is a company that focuses on solving the above problems.

Breakthrough in the technical difficulties of back-end and manufacturing EDA

What is EDA? Maybe everyone knows roughly what it is, but there are many different definitions. Generally speaking, according to different application scenarios, EDA is mainly divided into several major categories such as design, verification, and manufacturing. Specifically in the field of design, chip design can be divided into front-end (logical design) and back-end (physical design) based on physical realization.

Dr. Bai Geng showed the evolution of the "full process" tool concept in chip design in a previous speech, reflecting the development of the definition of EDA with the times.

He pointed out that the early "full process" was often only on the design side, that is, a more complete set of tools used by IC companies, and some tools on the manufacturing side were not included. At that time, verification tools, logic synthesis, placement and routing, sign-off timing and power, voltage drop, and other front-end tools, as well as physical verification, were called the full process.

But later, people began to pay attention to the manufacturability of chips, so yield tools were also added. In the past 5 years or so, people have begun to mention DTCO (Design Technology Co-Optimization) or STCO (System Technology Co-Optimization). OPC (Optical Proximity Correction) tools, reliability tools, and K library tools have also been included.

In the past two or three years, international manufacturers have also proposed a new "full process" concept - SLM (Silicon Lifecycle Management), which takes into account factors such as temperature, voltage, and environment that the chip may experience throughout its entire service life. It samples, analyzes, and optimizes the entire process from chip design to use, thereby enhancing the overall value of the chip product.

In my view, no matter what kind of concept is used and which type of tool is launched, the purpose of the chip industry using EDA is to improve design efficiency, enhance design reliability, and reduce costs. Therefore, based on the team's own background and experience, Guowei Xin aims to break through the technical difficulties of back-end and manufacturing EDA and join the research and development of domestic EDA.According to the introduction, through breakthroughs in core technology, Guowei Chip has made significant progress in the back-end and manufacturing end of EDA. For example, the company has independently developed a universal data base smDB, which supports industry-standard layout formats and has efficient memory utilization. This base will also serve as a common technology for Guowei Chip's "Xin Tiancheng" platform, achieving seamless connection between various tools, and significantly enhancing the layout loading capability.

As an EDA innovation enterprise with international competitiveness, relying on the advantages of independent and controllable core technologies, Guowei Chip has established an integrated platform of EDA + IP + design services. The main products and services include back-end EDA tools, manufacturing EDA tools, IP design, DFT design services, and back-end design services, providing safe, efficient, and convenient domestic EDA tool systems and services to global chip manufacturers.

Recently, Guowei Chip has released a number of self-developed digital EDA tools and software systems.

A number of self-developed EDA tools were released with great fanfare.

According to the introduction, the EDA tools released by Guowei Chip this time cover the core DRC tool of the physical verification platform - Xin Tiancheng Design Rule Check Tool EsseDRC, the upgraded version of the layout integration tool of the physical verification platform EsseDBScope (adding a powerful IP Merge function), the reliability platform Xin Tiancheng Reliability Timing Analysis Tool EsseChipRA, the connectivity check tool of the formal verification platform EsseCC, the model-based layout correction tool EsseMBOPC of the wafer manufacturing OPC platform, and the model-based verification tool EsseVerify. The following is an introduction to the technical highlights of these platforms:

1. Physical Verification Platform - Xin Tiancheng Design Rule Check Tool EsseDRC

The Xin Tiancheng Design Rule Check Tool EsseDRC released by Guowei Chip this time adopts key technologies such as distributed computing architecture, integrated high-performance unified data base, and high-efficiency geometric graphics calculation engine, which helps design engineers quickly locate DRC issues in the layout, linearly shorten the chip physical verification cycle, and accelerate the layout verification speed before product tape-out, providing a stable, accurate, and efficient physical verification solution for complex geometric shapes and advanced process design rules.

2. Physical Verification Platform - Xin Tiancheng Layout Integration Tool EsseDBScope

The Xin Tiancheng Layout Integration Tool EsseDBScope is a landmark tool developed based on Guowei Chip's EDA unified data base. The updated version launched this time adds functions such as IP merge, LVL, Signal tracing, and PG Find short. The product is based on an original data compression algorithm, supports data Hierarchy storage, and can achieve second-level opening of large-scale layout data; at the same time, it provides a powerful and easy-to-use script engine, realizing flexible customization and packaging of Pcells, and batch generation of Test patterns; the self-developed Boolean Engine provides efficient and stable graphics calculation, providing strong support for the processing and analysis of massive data. It integrates layout query, positioning, measurement, marking, and scaling functions, and supports fast Signal tracing, PG Find short, IP merge, Metal density, LVL, Boolean, and other data analysis and processing.

3. Reliability Platform - Xin Tiancheng Reliability Timing Analysis Tool EsseChipRATo meet the new requirements of chip timing analysis in high-reliability scenarios, Guowei Xin has developed the reliable timing analysis tool EsseChipRA. The product features a flexible and powerful reliability timing analysis engine that can cover the timing sign-off checks in chip design, estimation of aging conditions for automotive-grade chips, the impact of standard cell process fluctuations, and auxiliary timing constraints for layout and routing. It comprehensively considers the effects of aging and process fluctuations, working in conjunction with the aging library modeling module of the unit library extraction tool EsseChar, and the multi-process angle performance analysis optimization function of the unit library correctness checking tool EsseSanity, to accurately analyze and optimize the timing margin of the chip's critical path, thereby ensuring the functional correctness and stability of the chip design.

4. Formal Verification Platform - Guowei Xin Connectivity Check Tool EsseCC

Providing users with fast error detection and signal-to-signal verification needs for expected design behavior, Guowei Xin has launched its self-developed efficient connectivity check verification tool EsseCC. The product takes RTL circuits and connection specifications as input, quickly checks whether the design complies with the connection specifications, and can provide solutions for SOC/IO connectivity checks, post-synthesis Netlist connectivity checks, Chiplet technology module connectivity checks, as well as global clock and reset signal, bus register, integrated IP connectivity checks, etc.

5. Optical Proximity Correction Platform - Guowei Xin Model-Based Layout Correction Tool EsseMBOPC

To help customers perform efficient model-based optical proximity effect correction, customized local hot spot area correction, and etching effect compensation for all technology nodes, Guowei Xin has launched the model-based layout correction tool EsseMBOPC. Facing the challenge of shrinking process windows, EsseMBOPC can import the process window model to generate mask patterns that comply with manufacturing rules; improve lithographic imaging quality, making the lithographic image closer to the target pattern; and simultaneously enhance the lithographic process window to meet the yield requirements of semiconductor manufacturing.

EsseMBOPC has an accurate layout segmentation module and a strict built-in rule check engine (MRC), performing strict layout corrections, while also integrating AI and GPU acceleration technology, significantly improving computational speed, and helping users obtain the corrected patterns more quickly.

6. Optical Proximity Correction Platform - Guowei Xin Model-Based Verification Tool EsseVerify

To detect whether the mask correction results comply with manufacturing and lithographic rules, Guowei Xin has launched the model-based verification tool EsseVerify. The product can import models and generate lithographic simulation images, and the built-in detectors can quickly and efficiently capture various types of hot spots, helping engineers quickly perform mask pattern manufacturing rule checks, lithographic image quality checks, and effectively predict the lithographic process window to verify whether the OPC results meet the semiconductor process manufacturing and yield requirements.

Dr. Bai Geng said that the physical verification tool is one of the key R&D tools of Guowei Xin, and for this reason, the company's R&D process pays more attention to the underlying logic, which is where smDB plays an important role. He also emphasized that in the development process of different tools, the company has also integrated many new technologies to achieve two main goals: first, to accelerate the development efficiency of the product, ensuring that the company can quickly respond to customer needs in the market; second, to shorten the R&D and production cycle of customer chips, helping customers to quickly transform their designs into actual products.

Focusing on building a full-process EDA toolchain.According to the introduction, as of now, Guowei Xin has released five major series of products including the EssePV physical verification platform, the EsseOPC optical proximity correction platform, the EsseFormal formal verification platform, the EsseChar characterization modeling platform, and the EsseSimulation simulation verification platform, totaling 19 products, covering multiple core node tools at the design and manufacturing ends. The newly released products this time have enriched the tool sequence of Guowei Xin's "Xin Tiancheng" platform, accelerating the construction of the full process of domestic digital EDA, and helping manufacturers to achieve domestic substitution.

Looking ahead, Dr. Bai Geng emphasized the forward-looking development strategy of Guowei Xin. He pointed out that Guowei Xin's strategy is not limited to developing individual point tools, but focuses on building a full process EDA tool chain, which is consistent with the development trend of the three major international friends. "At the same time, we attach great importance to cooperation with IC design companies and foundries, gradually improving and perfecting tool functions through customer testing and verification to meet market demand." Dr. Bai Geng emphasized.

For Guowei Xin, the future will also adhere to the strategy of "independent research and development, absorption and introduction, industry-university-research integration, and investment and mergers and acquisitions" to build a "bridge" for the design and manufacturing of digital chips, deeply creating a full process EDA tool system for domestic digital chips, and achieving large-scale application, supporting the continuous and healthy development of the integrated circuit industry.