It is well known that chips are the core key and technical foundation of modern technology.

EDA, as a key link in the upstream of the integrated circuit industry chain, is an indispensable tool for designing large-scale integrated circuits and is known as the "mother of chips." It is also a recognized market with a small scale itself, but it can be a key "lever" to drive the semiconductor industry chain.

In recent years, with the turmoil and transformation of the global chip market, the construction of a strong, efficient, and innovative EDA ecosystem has become an urgent need in the industry.

Against this background and trend, on November 10th, at the ICCAD 2023 Summit Forum, Chen Yingren, the vice president of Shanghai Silicon Core Technology Co., Ltd. (hereinafter referred to as "Silicon Core"), brought a keynote speech titled "Win-win EDA New Ecology: Comprehensive Solutions and Diversified Cooperation". He shared excitingly around the topics of breaking through the industry of digital EDA, technological innovation, and how to build a new ecology of domestic EDA, and also highlighted the comprehensive solutions of Silicon Core in the field of digital EDA.

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Chen Yingren said that despite facing the market competition and siege from international giants, and facing many shortcomings such as technological accumulation, talent reserve, and lack of ecology, domestic EDA manufacturers have erupted like a bamboo shoot after a spring rain in recent years, with the strong support of policies and capital, the collaborative cooperation of industry chain partners, and the continuous breakthroughs of industry talents, facing difficulties.

He emphasized, "In the new ecology of EDA, in addition to pursuing economic returns, it is more important to focus on establishing deep cooperative relationships with partners based on 'benefit + righteousness'". The so-called benefit is the pursuit of benefits. The innovation of EDA technology can bring benefits to capital on the one hand, and on the other hand, it can help customers improve design efficiency, reduce costs, enhance competitiveness, and bring economic benefits to customers; righteousness is a new definition of win-win. EDA companies and partners are not only about economic benefits but more importantly, the joint undertaking of cooperation and responsibility.

It is not difficult to understand that EDA, in line with domestic technology, adheres to the principle of "benefit + righteousness", and creates a warm cooperative relationship, which is the foundation for building a new ecology of the EDA industry.

The new wave of technology promotes the innovation and transformation of EDA.At present, in addition to the efforts of local EDA manufacturers and industry partners to seek development, emerging technologies in the chip field are emerging one after another, and new architectures, standards, needs, and concepts are also continuously promoting industry progress. At present, RISC-V, Chiplet, and AI technologies have become high-frequency terms in the industry, and their development and maturity have brought new challenges and opportunities to EDA manufacturers.

Chen Yingren said that in the face of the rapid development of technologies such as RISC-V, AI, and Chiplet, EDA technology must innovate and transform to meet new design and implementation needs.

RISC-V brings more possibilities to design

First, let's look at RISC-V. The RISC-V architecture has abandoned the "historical baggage" in terms of design concepts, and has technical advantages such as simplicity, low power consumption, modularity, scalability, and open source, aiming to bring more possibilities to chip design.

Especially in the field of the Internet of Things (IoT), the emergence of the open-source architecture RISC-V has further ignited the enthusiasm of newcomers.

In the gradually maturing IoT industry, RISC-V has shown great potential with its highly diverse, low-power, high-security, and cost-effective advantages. More importantly, its open source and highly customizable features give chip design companies more autonomy, thus meeting the needs of diverse customers.

According to data from the RISC-V Foundation, in 2022, the processor cores using the RISC-V architecture have shipped 10 billion, most of which are concentrated in the MCU and IoT fields. It is expected that by 2025, the shipment of processor cores using the RISC-V architecture will exceed 80 billion. While the shipment volume is soaring, the application scenarios of RISC-V are no longer limited to the low-power IoT field, but are gradually expanding to application fields such as mobile phones, computers, automobiles, and data centers.

Moreover, as an open instruction set architecture, RISC-V also provides a new choice and opportunity for China's chip industry. With the intensification of international trade conflicts and "anti-globalization," the country has begun to accelerate the development of the open-source RISC-V architecture to avoid being at the mercy of others in mainstream CPU chip architectures, and to achieve more independent innovation and supply chain security.

Last year, the shipment of RISC-V architecture chips exceeded 10 billion, and the domestic shipment volume has already accounted for half. Not only have many domestic enterprises and research institutions joined the RISC-V International Foundation, but they have also established the China Open Instruction Ecosystem Alliance and the first domestic RISC-V patent alliance, dedicated to promoting the construction of China's RISC-V chip ecosystem.

RISC-V technology is redefining the future of computing with its openness, efficiency, and excellent scalability. However, the development of any technology has two sides. While RISC-V provides opportunities for independent supply chains and accelerates technological iteration, its open collaboration model also brings many challenges.The disadvantage of RISC-V lies in its early stage of development, where a comprehensive and unified technical system and business model have not yet been formed. Chen Yingren pointed out that RISC-V still has deficiencies in standard detail definition, fragmentation & stability, and EDA support, bringing challenges to chip design.

As RISC-V technology penetrates various fields, its open-source, simple, and highly scalable characteristics are gradually shaping the future. Despite the great potential of RISC-V, there are still areas in its ecosystem that need to be improved. In particular, its independent, flexible, and resilient design concept has greatly increased the problem of system fragmentation.

The task of EDA is to listen to customer needs to meet their support for product design or ecosystem in different applications.

To address these challenges, SileXin has provided a series of optimized solutions for RISC-V, covering micro-architecture analysis, system integration, specification compliance testing, and software performance evaluation. Through SileXin's "Xin Shen Jiang" system & application performance analysis, "Xin Shen Tong" assessment architecture configuration/software performance analysis, "Xin Shen Ding" specification compliance testing, and other strategies, a more efficient and stable RISC-V platform is constructed.

It is reported that SileXin is also helping the continuous evolution of the "Xiangshan" project of the Beijing Open Source Chip Research Institute.

"Xiangshan" high-performance RISC-V processor is an open-source project nurtured by the Institute of Computing Technology of the Chinese Academy of Sciences. From the first generation of "Xiangshan" to the current third generation, the technical support and evolution behind it are inseparable from the help of SileXin. The Open Chip Institute has adopted SileXin's "Xin Shen Tong" prototype verification solution to accelerate the evolution and application of its technology.

In the design of integrated circuits and microprocessors, prototype verification is an indispensable link, which involves verifying the functionality, performance, and reliability of the design on real hardware. SileXin has provided a targeted solution for "Xiangshan" - the Xin Shen Tong VU19P prototype verification system, enabling "Xiangshan" to efficiently complete SPEC score verification, IO verification, and the development of BSP drivers, covering various aspects from hardware design to software integration throughout the entire life cycle.

Chiplet technology: the solution for future computing power chips

In addition to RISC-V, the current development of Chiplet technology has also brought a new opportunity for domestic EDA manufacturers to "change the track and overtake."Chiplet, also known as "little chip" or "core grain," is a new form of IP reuse that integrates chips of different process nodes and materials into a system chip through advanced packaging technology.

In the chip industry, Chiplet has been favored by the industry because it can alleviate the limitations of performance, power consumption, and cost, greatly reducing the requirements and cost burden for the most advanced processes. Companies such as AMD and Intel have adopted the Chiplet solution to design chips, which is also known as "heterogeneous integration."

Similar to the RISC-V technology, the new trend of Chiplet also faces new challenges.

Chen Yingren said that under the trend of Chiplet, the addition of more heterogeneous chips and various buses will make the whole process more complex, and put forward new requirements for EDA tools. On the one hand, the design of the chip must adapt to the complex product form of different IPs and different Chiplet combinations, and the uniformity of interfaces and standards in the heterogeneous integrated system, and designers need to find a balance between the performance and flexibility of heterogeneous chips; on the other hand, Chiplet is reshaping the semiconductor industry chain, promoting new EDA tool chains, and combining new upstream and downstream ecosystems such as IP, design, backend packaging/production, and giving birth to new business models.

In response to such needs, the EDA industry has proposed a hybrid heterogeneous verification method. Mature Chiplets, RTL-Ready IP, and System Modeling IP can be modeled and verified simultaneously in a system, taking advantage of the high speed of Chiplets and RTL-Ready IP, and also supporting the flexible configuration function of System Modeling IP.

It is reported that for the needs of heterogeneous chip design verification, Sileixin has also proposed a unified verification platform based on the verification cloud system. The platform integrates different solutions such as architectural design and prototype verification to achieve efficient and fast verification.

AI + EDA: Adapting to the explosive growth of storage and computing power

In addition, under the new generation of generative AI wave led by ChatGPT, with the continuous growth of AI applications, while bringing new opportunities to the chip and EDA ecosystem, it has also triggered a surge in demand for computing infrastructure. As the foundation of computing power, the explosive growth of storage and computing power has put great pressure on SoC design and verification.

Chen Yingren said that the development of AI technology not only accelerates more complex computing needs, stronger functionality, and faster data transmission speeds, but also brings unprecedented challenges to chip researchers. Traditional chip design methods can no longer meet the current market demand; in addition, the AI engine changes the traditional von Neumann architecture, exploring application-driven algorithms, algorithm-driven software, and flexible collaborative design of hardware and software architecture under new framework requirements, leading the next innovation in chip design. The chip design industry urgently needs EDA innovation to cope with the new changes of the AI era.Particularly noteworthy is the increasing importance of verification throughout the entire process from design to tape-out, under the reality of the growing scale of integrated circuits. Effective verification not only ensures the perfection at the circuit design level but also guarantees its stable operation in practical applications, thereby reducing the cost and time for corrections and adjustments.

To meet this challenge and shorten the verification cycle, hardware simulation has become a key tool for the verification of ultra-large scale integrated circuits. At the same time, the rapid growth of AI computing power has not only promoted the rapid evolution of EDA tools but also combined with EDA tools to create a virtuous cycle of "dual acceleration."

In response, S2C launched the first domestic enterprise-level hardware simulation system - the OmniArk, which adopts an AI-driven intelligent compilation engine. This hardware simulation system can greatly reduce compilation time and memory occupation during the compilation process, achieve incremental compilation, and intelligently match P&R strategies, thereby significantly improving the success rate of wiring.

OmniArk applies AI to the compilation process, promoting the development of the chip design field and ushering in a new era of EDA verification.

In addition, S2C's X-Eye logic system and logic module products are also highly competitive prototype verification solutions in the current market, and their cost-effectiveness has been favored by the market. Not long ago, S2C released the latest generation of prototype verification solutions - the X-Eye logic system S8-40, which also provides effective solutions for current designs with large storage and big data such as AI and GPU chips.

S2C, 20 years of continuous creation of the full digital EDA process.

Overall, in the face of the rapid progress of technologies such as RISC-V, Chiplet, and AI, EDA technology must innovate and transform to meet new design and implementation needs.

Under the industry opportunities and challenges led by new technologies, S2C is committed to creating innovative business models through the layout of new technologies, forward-looking exploration, and focusing on application innovation, soft and hard interaction, and system engineering to create greater value for customers.

Chen Yingren introduced that in the face of the above new technologies' demands for convenience and accuracy, S2C's tools, as carriers and platforms, can explore the virtual and real architecture of new technologies, combining with different EDA manufacturers, IP manufacturers, backend manufacturing, and other industrial chain partners to provide more effective solutions for customers.It is understood that Sile Xin was established in Shanghai in 2004. Over the past 20 years, Sile Xin has continued to leverage its advantages in EDA technology, and has been committed to providing a comprehensive, full-process, and full-coverage product portfolio for numerous IC design companies. Chen Yingren stated that Sile Xin focuses on the digital front-end field of chips, and has launched a series of high-quality digital EDA tools, such as the architectural design tool "Xin Shen Jiang", the software simulation tool "Xin Shen Chi", the hardware simulation tool "Xin Shen Ding", the prototype verification tool "Xin Shen Tong", as well as providing comprehensive EDA cloud services, to ensure that the chip design process can fully and accurately respond to the requirements of the specifications, thereby accelerating the development process of chip products.

At present, the trend of EDA gradually moving to the cloud is becoming more and more evident. Sile Xin is the first EDA company in China to launch prototype verification cloud services through independent research and development.

At the ICCAD forum, Professor Wei Shaojun, the chairman of the Integrated Circuit Design Branch of the China Semiconductor Industry Association, said that in 2023, there are 3,451 chip design companies in mainland China, an increase of 208 from last year. However, these 3,451 chip design companies are widely distributed across various industries such as consumer electronics, industry, automotive, data centers, etc. Most of these companies are small and medium-sized enterprises, and most of them are facing problems such as a shortage of personnel and a lack of design capabilities, especially when the design team is performing simulation and verification, they often lack the support of large-scale computing power clusters.

For applications with higher requirements for chip design, such as AI and HPC, not only does it put forward requirements for the innovation of the development team, but it also puts forward higher requirements for their hardware computing resources, so the clouding of software has been proposed. The continuously expandable computing resources provide convenience for design and verification, greatly reducing the efficiency of chip design automation, and also reducing the cost of infrastructure addition and management.

Under this trend, EDA manufacturers have successively started their own journey to the cloud, developing cloud-based EDA businesses.

Sile Xin released its self-developed digital circuit debugging software "Xin Shen Jue"

At the same time, at ICCAD 2023, Sile Xin officially released a self-developed digital circuit debugging software - "Xin Shen Jue". This brand-new tool integrates core functions such as source code tracking, waveform debugging, schematic extraction, and coverage analysis, aiming to provide engineers with a comprehensive and efficient analysis and debugging platform. Advanced debugging technology helps developers simplify the entire debugging process and accelerate chip development.

"Xin Shen Jue", after flexible connection with other products of Sile Xin such as software simulation, hardware simulation, and prototype verification, achieves deep integration, and can create a unified and efficient design environment for chip engineers. This not only greatly simplifies the complex debugging work but also makes the entire debugging process more smooth and efficient, significantly improving the efficiency of complex chip design verification.Sierxin's technical strength in the EDA field has been widely recognized by the industry. Through years of dedication, it has established a dual advantage in technology and market in the digital front-end EDA field and has established good cooperative relationships with more than 600 domestic and foreign enterprises. It has participated in the formulation of China's EDA group standards, undertaken a number of national and local major scientific research projects, and won many honors and qualifications such as the national "Little Giant" enterprise with specialized, refined, and innovative characteristics, the national outstanding industrial software product, and the Shanghai municipal-level enterprise technology center.

With the launch of the new "Xin Shen Jue" product, it will further enhance the digital front-end EDA solutions of Sierxin, providing chip design enterprises with a more comprehensive set of products and services.

In conclusion, as the "foundation technology" in the field of chip design, under the promotion of new technology trends such as RISC-V, Chiplet, and AI, the full-process innovation of EDA will drive significant changes in the chip industry.

At the same time, as the world's largest and fastest-growing integrated circuit market, China's domestic EDA is facing a huge development space and market potential under the complex international trade relations and the trend of "domestic substitution."

Many opportunities promote development, and the future of domestic EDA is promising.

In this process, domestic EDA enterprises represented by Sierxin are focusing on the path to breaking through the EDA industry, striving to create a new ecology of domestic EDA.